1. Field of Invention
The present invention relates generally to integrated circuit packaging and, more particularly, to a low cost routable substrate that overcomes wire length, die size, and high cost constraints typically found in other solutions such as TAPP (thin array plastic package), HMT, WPLGA and tsCSP (thin substrate chip scale package), and may used in relation to the manufacture of Dual and Quad Flat No-Lead (DFN/QFN) style semiconductor packages as a substrate or interposer of such packages.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal lead frame, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the lead frame, bond wires which electrically connect pads on the semiconductor die to individual leads of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The lead frame is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the lead frame is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the lead frame extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component.
For purposes of high-volume, low-cost production of semiconductor packages, a current industry practice is to etch or stamp a thin sheet of metal material to form a panel or strip which defines multiple lead frames. A single strip may be formed to include multiple arrays, with each such array including a multiplicity of lead frames in a particular pattern. In a typical semiconductor package manufacturing process, the integrated circuit dies are mounted and wire bonded to respective ones of the lead frames, with the encapsulant material then being applied to the strip so as to encapsulate the integrated circuit dies, bond wires, and portions of each of the lead frames in the above-described manner. Upon the hardening of the encapsulant material, the lead frames within the strip are cut apart or singulated for purposes of producing the individual semiconductor packages. Such singulation is typically accomplished via a saw singulation process. In this process, a saw blade is advanced along “saw streets” which extend in prescribed patterns between the lead frames as required to facilitate the separation of the lead frames from each other in the required manner.
With particular regard to DFN/QFN style semiconductor packages, current methods used to manufacture saw singulated DFN/QFN semiconductor packages involve the use of a lead frame to which integrated circuits or die are mounted using epoxy. Once the die or integrated circuit(s) is/are mounted to the lead frame, the interconnections between the die and the leads of the lead frame are typically made using thermosonic gold ball bonding methods. The integrated circuits are then encapsulated using epoxy mold compound. After encapsulation, the integrated circuits are singulated using a sawing process as described above.
These DFN/QFN packages typically utilize a copper based lead frame in which the pattern representing the leads and die attach pad or die pad (to which the die is typically attached) are etched. The leads and die pad each usually contain design features that aid in locking to the epoxy mold encapsulant or package body. For example, locking features found on a lead are typically created by selectively half etching portions of the bottom side of the lead. This creates a lead structure in which the top portion is substantially larger than the bottom portion. When encapsulated, this prevents the lead from being pulled out of the package during expected use conditions.
As also indicated above, individual units are normally arranged in an array pattern to maximize the number of units on a strip. All the units in the strip are held together by use of common copper features called a connecting bar that is later removed during the package singulation process. To aid in manufacturing, temperature resistant tape is usually mounted to the bottom side of the strip. This tape helps stabilize the strip during the wire bonding process by allowing vacuum clamping. The tape also prevents mold flash from occurring during encapsulation.
There are several drawbacks to this tape based lead frame structure. First, the connecting bars that hold the units together in the strip must be removed during the singulation process. The diamond abrasive blades typically used must saw through both the encapsulant and the metal connecting bars. Because of the metal, this requires a slower cutting speed and decreases blade life. By removing metal from the singulation path, saw speed and blade life can be increased and result in lower costs.
Second, the use of tape to help stabilize the leads for wire bonding does impose limitations on what can be bonded to. For example, the leads usually have half etch features on top of the leads but no supporting metal structure underneath. Because there is normally a gap between the tape and these features, these features cannot be bonded to due to lack of physical support underneath. This generally limits bonding to areas of full metal thickness that are supported directly underneath by tape.
Third, the requirement for all design features such as leads, die pads, etc., to be connected together prevents electrical testing the individual units in strip form without additional manufacturing complexities required to electrically isolate the leads. For example, in conventional tape based DFN/QFN lead frames, an isolation saw cut is required to isolate the leads from the connecting bars, but without cutting through the full thickness. A means of creating electrically isolated leads in a strip design without adding manufacturing complexity would create advantages in electrical testing in strip form.
Finally, routable versions of TAPP, WPLGA and tsCSP all utilize a plate-up process over a dielectric to create such routable version. All of these versions require a sacrificial layer that is removed after the package body molding step. While they can accomplish the need for routing, they are all high cost solutions due to the additive process used.
The present invention, as described below, provides a low cost routable substrate that addresses the various drawbacks discussed above which are typically found in other solutions such as TAPP, HMT, WPLGA and tsCSP, and may used in relation to the manufacture of Dual and Quad Flat No-Lead (DFN/QFN) style semiconductor packages as a substrate or interposer of such packages